1. Field of the Invention
The present invention relates to a parallel read circuit for testing high density semiconductor memories, and particularly to a parallel read circuit which reads out a larger quantity of data not dependent on the number of data buses in the chip under test by parallelly reading out plural bits of data from the memory cells provided with test pattern inputs for checking any existence of disorder in the manufactured high density memory chips, thereby effectively reducing the required testing time.
2. Description of the Art
Recently in the semiconductor-related manufacturing field, semiconductor memory elements with low power consumption, high operational speeds and high density have become of interest in accordance with advances in data information communication. A high level of manufacturing technology is required to produce such high density memories, and such memory scale requires a quality test before the products are shipped. However, the higher the density of the memory cell within a single chip, the more complicated the testing procedure for the cell. Furthermore, a more lengthy time is required for carrying out the testing. The required test time per circuit is related to productivity, and therefore, efforts for improving testing efficiencies is becoming of interest in direct relationship with increasing chip densitites.
Thus, testability (so called in the art), which includes controllability (the ability of controlling the internal structure from the input terminal of chip) and observability (the ability of observing the functional state of the internal structure from the output terminal of chip), needed to be increased.
However, viewed from economies of scale, which is the subject of the present invention, the conventional test scheme is constituted such that, in order to provide a minimum economy of scale especially for RAM (random access memory) elements, plural bits of data outputted from each cell array block are extracted one by one by means of a multiplexer; these bits are supplied through respective data buses to a comparator which is situated at an input terminal of an output buffer; this comparator compares the output data read from a predetermined data test pattern, thereby detecting any malfunction of any cell.
According to this scheme, one data bus can carry one data stream, and therefore, where plural bits of data are parallelly read out from respective cell arrays, the testable number of bits of data is limited to the number of the data buses extant, resulting in restriction of the time required to carrying out the testing of the array. This problem becomes more serious as the density of the memory elements increases.